1. Field of the Invention
The present invention relates to an all-in-one polishing process for a semiconductor wafer, and more specifically, to a method of performing two chemical mechanical polishing (CMP) processes to respectively polish a top surface and an edge bevel surface of the semiconductor wafer, and performing a cleaning process and a drying process thereafter.
2. Description of the Prior Art
Chemical mechanical polishing (CMP) is a method of polishing materials, such as a semiconductor wafer, to a high degree of planarity and uniformity. The process is used to planarize a semiconductor wafer prior to the fabrication of microelectronic circuitry thereon, and is also used to remove high-elevation features created during the fabrication of the microelectronic circuitry on the surface of the semiconductor wafer.
Please refer to FIG. 1 and FIG. 2, which respectively present a top view and a cross-sectional view of a semiconductor wafer 10 according to the prior art. As shown in FIG. 1 and FIG. 2, the semiconductor wafer 10 comprises a top surface 10a, an edge bevel surface 10b and a bottom surface 10c, and the edge bevel surface 10b comprises a front side bevel 10b1, a backside bevel 10b2 and an edge 10b3. The top surface 10a comprises at least a first material layer 12, comprising at least a semiconductor structure (not shown), such as a dual damascene structure or a capacitor structure, on the top surface 10a, and the edge bevel surface 10b comprises a second material layer 14, either spontaneously formed with the first material layer 12 or formed prior to the formation of the first material layer 12, needing to be completely removed due to the product specification. Either the first material layer 12 or the second material layer 14 comprises either a dielectric layer or a metal layer, and is formed by performing either a chemical vapor deposition (CVD) process or an electric copper plating (ECP) process. In the preferred embodiment of the present invention, the first material layer 12 and the second material layer 14 are respectively composed of two different materials. Alternatively, the first material layer 12 and the second material layer 14 are composed of a same material. In addition, the edge 10b3 of the semiconductor wafer 10 comprises a notch 16 for locating the coordination of the semiconductor wafer 10 during the polishing and cleaning of the semiconductor wafer 10.
Please refer to FIG. 3 of a schematic view of a chemical mechanical polishing device (CMP device) 20 according to the prior art. As shown in FIG. 3, the CMP device comprises a polishing plate 22, a polishing pad 24 disposed on the polishing plate 22, a head 28 for pressing the semiconductor wafer 10 onto the polishing pad 24, a slurry supply tube 30, a cleaning solution supply tube 26 and a conditioner 32 for controlling the polishing pad 24 and removing flakes generated during polishing of the semiconductor wafer 10. The head 28 comprises a holder (not shown) for containing the semiconductor wafer 10, the slurry supply tube 30 provides slurry on the semiconductor wafer during the polishing of the semiconductor wafer 10, and the cleaning solution supply tube 26 provides either a cleaning solution (not shown) or deionized water (DI water, not shown), during the cleaning of the semiconductor wafer 10 and the polishing pad 24.
The method of polishing and cleaning the semiconductor wafer 10 according to the prior art begins with adding the slurry on the top surface 10a of the semiconductor wafer 10. A CMP process is then performed by utilizing the polishing pad 24 of the CMP device to polishing portions of the first material layer 12 down to a first thickness based on the produce requirement, and the semiconductor wafer is sent to a buffing pad (not shown) softer than the polishing pad 24 thereafter. A buffing process, utilizing either the cleaning solution or DI wafer provided by the cleaning solution supply tube 26, is then performed to remove flakes of the first material layer 12 and residual slurry on the top surface 10a of the semiconductor wafer 10.
Finally, a chemical cleaning process and a drying process are performed to clean and dry the semiconductor wafer 10, as shown in FIG. 4 of the cross-sectional view of the polished and cleaning semiconductor wafer 10.
However, as shown in FIG. 4, the second material layer 14 needing to be completely removed remains on the edge bevel surface 10b after portions of the first material layer 12 are removed down to the first thickness and the cleaning process is performed to cleaning the semiconductor wafer 10. Pealing of the remaining second material layer 14 frequently occurs in subsequent process due to thermal stress or other reasons, leading to the cracking of the second material layer 14. Flakes and particles of the second material layer 14 caused by the cracking thereof frequently fall on and therefore contaminate a top surface of another semiconductor wafer adjacent to the semiconductor wafer 10 during either a CVD process or the transportation of a batch of semiconductor wafers, making the performance of the product defective.